The disclosures herein relate generally to processors, and more specifically, to processors that employ clock cycle variability software for design modeling and analysis.
Modern information handling systems (IHSs) often encounter significant design model evaluation testing and analysis prior to implementation in hardware. One such test is the high frequency clock verification of digital design models. Designers or other entities must take into account clock jitter and duty cycle variability when performing clock frequency verification tests, such as a static timing analysis (STA) on design models. Designers evaluate a particular hardware design to determine if clock jitter, duty cycle variability, and other factors cause the hardware design to function with good or bad results at desirable clock frequencies.
One method that designers use for clock frequency verification is a storage element and slack analysis of the devices of a hardware design. In this case, designers generate a design model of a hardware design that includes data paths of devices in the hardware design. A data path may employ a series of devices that launch a particular data bit, pass that data bit through one or more delay devices, and capture that data bit at the end of the data path with a final storage element. In this manner, STA software may generate slack data for each data path of the design model during STA evaluation. Slack is the measure of the amount of margin in time that a particular data path exhibits for a particular clock frequency, such as that of a main clock for data that propagates through that particular data path. The evaluation of half and full cycle data paths is critical to modern hardware design. A half cycle data path is a data path that employs a pulse width of one half cycle of the main clock during STA evaluation. A full cycle data path is a data path that employs the main clock full period or full cycle during STA evaluation.